
module tx_buf_4_8_64(
    input                                   clk_i,
    input                                   rstn_i,

    input                                   wen_i,
    input   [31:0]                          waddr_i,
    input   [31:0]                          wdata_i,

    input   [7:0]                           raddr_i,
    output reg[7:0]                         rdata_o   
);

reg                 wen_0  , wen_1  , wen_2  , wen_3  ;
wire [7:0]          wdata_0, wdata_1, wdata_2, wdata_3;
wire [7:0]          rdata_0, rdata_1, rdata_2, rdata_3;

wire [1:0]          wByte_sel;
wire [5:0]          waddr;

wire [1:0]          rByte_sel;
wire [5:0]          raddr;

assign waddr     = waddr_i[7:2];
assign wByte_sel = waddr_i[1:0];

assign raddr     = raddr_i[7:2];
assign rByte_sel = raddr_i[1:0];

always@(*)begin
    case (wByte_sel)
        2'b00 : begin
            wen_0 = wen_i;
            wen_1 = wen_i;
            wen_2 = wen_i;
            wen_3 = wen_i;
        end
        2'b01 : begin
            wen_0 = 1'b0 ;
            wen_1 = wen_i;
            wen_2 = wen_i;
            wen_3 = wen_i;
        end
        2'b10 : begin
            wen_0 = 1'b0 ;
            wen_1 = 1'b0 ;
            wen_2 = wen_i;
            wen_3 = wen_i;
        end
        2'b11 : begin
            wen_0 = 1'b0 ;
            wen_1 = 1'b0 ;
            wen_2 = 1'b0 ;
            wen_3 = wen_i;
        end
        default: begin
            wen_0 = wen_i;
            wen_1 = wen_i;
            wen_2 = wen_i;
            wen_3 = wen_i;
        end
    endcase
end

// 小端存储
assign wdata_0   = wdata_i[7 :0 ];
assign wdata_1   = wdata_i[15:8 ];
assign wdata_2   = wdata_i[23:16];
assign wdata_3   = wdata_i[31:24]; 

// 输出读数据选通
always@(*)begin
    case (rByte_sel)
        2'b00  : rdata_o = rdata_3;
        2'b01  : rdata_o = rdata_2;
        2'b10  : rdata_o = rdata_1;
        2'b11  : rdata_o = rdata_0; 
        default: rdata_o = rdata_3; 
    endcase
end

// 第一字节
spi_ram_8b_64 u_ram_0(
    .clk_i      (   clk_i   ),
    .rstn_i     (   rstn_i  ),

    .wen_i      (   wen_0   ),
    .waddr_i    (   waddr   ),   
    .wdata_i    (   wdata_0 ),

    .raddr_i    (   raddr   ),
    .rdata_o    (   rdata_0 )                         
);

// 第二字节
spi_ram_8b_64 u_ram_1(
    .clk_i      (   clk_i   ),
    .rstn_i     (   rstn_i  ),

    .wen_i      (   wen_1   ),
    .waddr_i    (   waddr   ),   
    .wdata_i    (   wdata_1 ),

    .raddr_i    (   raddr   ),
    .rdata_o    (   rdata_1 )                         
);

// 第三字节 
spi_ram_8b_64 u_ram_2(
    .clk_i      (   clk_i   ),
    .rstn_i     (   rstn_i  ),

    .wen_i      (   wen_2   ),
    .waddr_i    (   waddr   ),   
    .wdata_i    (   wdata_2 ),

    .raddr_i    (   raddr   ),
    .rdata_o    (   rdata_2 )                         
);

// 第四字节
spi_ram_8b_64 u_ram_3(
    .clk_i      (   clk_i   ),
    .rstn_i     (   rstn_i  ),

    .wen_i      (   wen_3   ),
    .waddr_i    (   waddr   ),   
    .wdata_i    (   wdata_3 ),

    .raddr_i    (   raddr   ),
    .rdata_o    (   rdata_3 )                         
);
endmodule